This invention relates to display control apparatuses and methods for controlling display devices. The apparatuses receive image data, which is transmitted from an image source, in synchronous with input clock signal and output the image data to display devices in synchronous with output clock signal, which may be asynchronous with the input clock signal.
Image sources such as personal computers and various visual apparatuses may be connected to image display devices such as liquid crystal displays via digital image input/output interfaces based on various standards such as DisplayPort. The image source transmits packets that include image data, audio data, synchronizing signals, and the like, to the image display device.
In DisplayPort standard described above, image data is transmitted in synchronous with an input clock signal CLK1. Further, values M and N (each of M and N is a positive integer) are transmitted in order to enable the image display apparatus to generate an output clock signal CLK2, which has a relationship that N*(a cycle period of CLK1)=M*(a cycle period of CLK2). The values M and N are transmitted periodically to the image display apparatus so that the relationship between the clock signals CLK1 and CLK2 are updated periodically.
Accordingly, an image display devices may be accompanied with a display control apparatus including a clock generation circuit that generates the output clock signal CLK2 based on the input clock signal CLK1 and the values M and N received from the image source. The display control apparatus may further include circuitry to convert the image signal received in synchronous with the input clock signal CLK1 into an output signal to be supplied to the image display device in synchronous with the output clock signal CLK2.
U.S. Pat. No. 6,992,987 (Patent Document 1) discloses to recover clock signal CLK2 from clock signal CLK1 and the values M and N. Specifically, Patent Document 1 discloses to recover pixel and audio clock signals from a link clock signal by expressing the pixel and audio clock rates and the link clock rates using four parameters A, B, C, and D based on a master clock signal of 23.76 GHz, which is represented by 210×33×57×111 Hz.
As explained above, the cycle period of the output clock signal CLK2 is N/M times the cycle period of the input clock signal. However, there may be cases that the values M and N cannot be accurately expressed within an available number of bits. Thus, approximate values of M and N are transmitted. Further, when the input clock signal, which is used as a transmission clock, is spectrum spread, it is impossible to accurately determine the values of M and N. Thus, average values M and N may be transmitted.
When the output clock signal is generated based on such approximate or average values of M and N, the output clock becomes asynchronous with the input clock signal. That is, for example, a period of a frame measured based on the cycle period of the input clock signal may become different from a period of the frame measured based on the cycle period of the output clock signal. As a result, timings of edges of the input and output clock signals at the beginning of each frame becomes different with each other, and the amount of difference between the timings changes from a frame to another frame.
This change may be accumulated during successive frames and may generate an excessively large timing difference. As a result, the capacity of a buffer memory that absorbs the difference between the input and output timings of the image data may become insufficient, and the displayed image may be disturbed or it becomes impossible to display the image.
It is also possible to detect an edge of the output clock signal at the timing of a signal synchronized with the input clock signal, and determine a start timing of each of the lines of the output image. In this case, the difference, or the latency, between the input and output timings of the image data do not accumulate. However, the number of cycles of the output clock signal per line may change from a line to another line. If the number of cycles of pixel clock per line changes, the displayed image may be disturbed.